Microelectronic imagers are used in a multitude of electronic devices. As microelectronic imagers have decreased in size and improvements have been made with respect to image quality and resolution, they have become commonplace devices and are used, for example, in computers, mobile telephones, and personal digital assistants (PDAs), in addition to their traditional uses in digital cameras.
Microelectronic imagers include image sensors that typically use charged coupled device (CCD) systems and complementary metal-oxide semiconductor (CMOS) systems, as well as other solid state imager systems.
Microelectronic imager modules, such as module 150 shown in FIG. 1, are often fabricated at a wafer level in which many such modules are formed as part of a wafer assembly and then separated. The imager module 150 includes an imager die 108, which includes an imager pixel array 106 and associated circuits (not shown). Imager pixel array 106 may be a CCD or CMOS imager pixel array, or any other type of solid state imager pixel array. Imager module 150 may also include a lens structure 112, having a spacer 109 and at least one lens element 111 arranged on a portion of a lens wafer 510. Spacer 109 maintains lens element 111 at a proper distance from imager pixel array 106, such that light striking lens element 111 is directed appropriately to imager pixel array 106. Spacer 109 may be bonded to imager die 108 by a bonding material 104 such as epoxy. Typically, lens element 111 comprises one or more optically transmissive lenses made of glass or plastic material configured to focus light radiation onto imager pixel array 106. In addition, the lens structure 112 may be combined with another optically transmissive element, such as a package lid.
In practice, imager modules 150 are fabricated at a wafer level in mass rather than individually. As shown in a top-down view in FIG. 2A and a cross-sectional view in FIG. 2B—both FIGS. showing a portion of a larger wafer assembly—multiple imager dies 108a-108d (four shown here for simplified illustration) are fabricated on a semiconductor wafer 90. Each die includes a respective imager pixel array (FIG. 2B illustrates two arrays 106a, 106b because it is a cross-sectional view). As shown in FIGS. 3A and 3B, multiple lens elements 111a-111d (again, four shown here for simplified illustration), corresponding in number and location to the imager pixel arrays 106 on imager wafer 90 (FIGS. 2A and 2B), may be fabricated on a lens wafer 510. A replication process, for example an ultraviolet embossing, can be used to duplicate the surface topology of a lens master onto a thin film of an ultraviolet-curable epoxy resin applied to lens wafer 510. As shown in FIG. 4A, lens wafer 510 is placed so that it is separated from imager wafer 90 by spacers 109, the latter typically formed on a separate spacer wafer. Additionally, lens wafer 510 is located such that lens elements 111a-111d (FIG. 4A illustrates only 111a and 111b because it is a cross-sectional view) are optically aligned with imager dies 108a-108d (FIG. 4A illustrates only 108a and 108b because it is a cross-sectional view) to form a plurality of imager modules 150a, 150b (other imager modules are formed, but not shown in FIG. 4A). As shown in FIG. 4C, the imager modules 150a, 150b may then be separated into individual imager modules 150a, 150b by dicing.
One technique for creating the spacers 109 is to place a mask over a glass or polymer wafer material used for spacer 109 prior to using fine-grit sand to blast through these non-masked portions of the glass or polymer wafer. This creates a through-hole spacer 109. Another technique for creating a through-hole spacer 109 is to place an etch stop material over a glass or polymer wafer and apply an etching material that removes the glass or polymer in those portions where the etch stop material is not present. Both of these techniques have shortfalls. Primarily, both techniques can result in a through-hole that has at least some taper resulting from a greater application of either fine-grit sand or etching material to the portion of the hole closest to where the removal media is being applied. This taper can appear where non-tapered through-holes are required, or can more greatly exaggerate a desired taper. Accordingly, a method of fabrication of spacers 109 is required where the dimensions of the spacer can be more precisely maintained.
In addition to fabrication problems, the fabrication of spacers 109 on a separate wafer introduces additional steps into the imager assembly process. Currently when assembling an imager, the spacer 109 wafer must be aligned over the imager wafer 90, and the lens wafer 510 must then be aligned over the spacer 109 wafer. This creates multiple opportunities for misalignment.
Referring now to FIG. 4B, in cases where multiple lenses (stacked over one another) are required, an additional spacer 109a wafer must be placed over lens wafer 510, and an additional lens wafer 510a with lens elements 111e-111f must be placed over the additional level of spacers 109a. With each additional lens element that must be added to the imager module fabrication becomes even more complex, and the likelihood of misalignment further increases.
Accordingly, there is a need for an apparatus and method that provides through holes that have reduced inadvertent tapering during formation of the spacers, reduces the assembly steps necessary for both single- and multi-lens imagers, and reduces the likelihood of misalignment for both single- and multi-lens imagers.